The present invention relates generally to methods and apparatus for operating multiprocessor systems, especially numerical control systems, and more specifically, to such a method and apparatus in which the individual processors have access to the bus on a priority basis that is controlled by bus arbiters that control bus coupling elements that interface with the processors, and where the bus requests during each processing cycle occur in blocks.
Multiprocessor systems can be used for the most varied purposes in numerical controls for machine tools and robots. For example, it is possible to use several processors for the position control of the axes to be traveled, such as one processor per axis. The operation of these processors on a common bus system of this type is disclosed in DE-OS 35 01 968.
In numerical control technology, usually all of the processors are coordinated by a common time signal which determines the processing cycle. At the cycling time the processors request the common bus, as needed. This access is arbitrated to avoid bus conflicts. Processors with priority, e.g. master processors, are treated with preference over subordinate processors, e.g. slave processors. Therefore, the slave processors must wait until the processors with priority withdraw their bus requests. During the waiting time, however, a processor cannot perform any other tasks. The processing output of the entire system is therefore reduced by this waiting time.
It is more advantageous if the individual accesses to the bus by the processors, during normal operation, occur according to a "time slice principle," (i.e. time domain multiplexing), because then the waiting times, which reduce operation time, are eliminated.
A time slice principle is disclosed in DE application 39 32 590. In this fixed time slice operation, however, the borders of the time slices have to be selected in such a way that there are absolutely no overlaps of the time slices. Accordingly, the operation of the processors must always occur according to the strict rules of the time slices, so that no conflicts occur, since these cannot be tolerated within this system.
The present invention is directed to the problem of developing a multiprocessor apparatus that uses bus arbiters as bus access controllers that operate according to the time slice principle, which reduces the waiting times extensively, and which does not require strict time slice boundaries.